1. Field of the Invention
The present invention relates to an array substrate for a flat display device and a method of fabricating the same.
2. Description of the Related Art
With the development of information society, the requirements of display devices for displaying an image have increased in various forms, and in recent years, various flat display devices have been used such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED), an electrophoretic display device (EPD), and the like.
For example, an electrophoretic display device has features such as no external light source, excellent flexibility and portability, light weight, and the like.
Such an electrophoretic display device is a reflective type display in which a thin-film transistor array substrate is formed on a thin and flexible base film such as paper or plastic and a transparent conductive layer is coated to drive suspended electrophoretic particles, and expected to be widely used as a next-generation electronic paper.
FIG. 1 is a view illustrating an electrophoretic display device in the related art, and FIG. 2 is an enlarged view illustrating a portion “A” of FIG. 1.
Referring to FIG. 1, an array substrate of the electrophoretic display device may include a data pad portion 20 and a gate pad portion 30 located at an edge region of the substrate 10, namely, non-display region. Furthermore, a plurality of data lines formed on the display region are linked to the data pad portion 20, and a plurality of gate lines formed on the display region are linked to the gate pad portion 30. A plurality of gate pads (not shown) and data pads (not shown) are formed on the gate pad portion 30 and data pad portion 20 and linked to the gate lines and data lines one to one. In the display region, a plurality of gate lines 35 and a plurality of data lines 25 are vertically crossed with each other to define a plurality of unit pixels (P's).
Gate and data signals from a driving circuit unit (not shown) are applied to each pixel of the display region. FIG. 2 is an enlarged view illustrating a portion “A” of FIG. 1, and schematically illustrates a link portion of the non-display region. In particular, FIG. 2 illustrates data link lines 22_1 to 22_3 of the non-display region for applying data signals from the driving circuit unit (not shown) to each pixel (P). In this case, an electrostatic discharge protection circuit (not shown) may be further provided between the unit pixel (P) and data link lines 22_1 to 22_3.
Furthermore, the data link lines 22_1 to 22_3 from the driving circuit unit are arranged in parallel with one another in the non-display region, wherein each data link line is bent in the vertical direction (that is, bent at 90° with respect to a portion thereof extending from the driving circuit unit) and linked to the corresponding data line to enter the display region.
A current technological trend is aimed at decreasing the bezel to increase a visual sense of beauty, and thus the development of displays with a narrow bezel have been carried out. Displays with a narrow bezel have a narrow non-display region and thus the gaps between the data link lines disposed in the non-display region as well as the line width of the data link lines may be decreased, thereby increasing resistance to cause a problem of signal delay. If the delay of a signal applied to the data link lines is significantly increased due to the resistance of the data link lines, then a ghost phenomenon may occur in which the previous image remains while the current image is updated to the next image.